1. Field of the Invention
The present invention relates to an alignment method for precisely aligning a plurality of areas on substrates to be aligned with predetermined reference positions in a device requiring precise alignment, such as a contraction projection type exposure apparatus in which an electronic circuit pattern is projected onto a semiconductor substrate for exposure.
2. Description of Related Art
The development of highly integrated semiconductors, in recent years, has caused the dimensions of the semiconductor device pattern to be of the order of a submicron, so that technical developments have been carried out extensively for more precise alignment of the mask and the wafer in a semiconductor exposure apparatus.
As a semiconductor exposure device, a so-called stepper of the contraction projection type is widely used. FIG. 5a schematically illustrates an example of a contraction projection type semiconductor exposure device.
Referring to the figure, a light beam from an exposure illuminating system (not illustrated) illuminates an electronic circuit pattern formed on a reticle R. The illuminated pattern is projected onto a wafer W for exposure through a projection optical system 1. Wafer W is placed on a stage 11 movable two-dimensionally along the X and Y planes. S denotes an alignment optical system, which detects a position along the x dimension in the figure. A similar alignment optical system (not illustrated) is also provided, which detects a position along the y dimension. A CPU 9 (central processing unit) controls the operation of the entire exposure apparatus.
The alignment of the wafer W relative to the reticle R is carried out before exposure by the following process. When wafer W is placed onto XY stage 11 by a wafer transporting device (not illustrated), CPU 9 generates a command to a stage driver 10 such that, as illustrated in FIG. 6, alignment marks M1x and M1y of shot area S1 are positioned within the field of view of alignment optical system S, thereby causing XY stage 11 to be driven. An alignment illuminating device 2 irradiates wafer W with a light beam which does not cause exposure nor photosensitization of a resist (photosensitization agent) coated on the wafer W, and the light beam illuminates an alignment mark M1x (hereinafter referred to as wafer mark) through a beam splitter 3, reticle R and projection optical system 1.
FIG. 5b illustrates this wafer mark M1x in detail, wherein a plurality of marks having the same rectangular shape are disposed at a constant pitch of .lambda.p. A light beam reflected from wafer mark M1x reaches the beam splitter 3 by passing through, once again, projection optical system 1 and reticle R, where it is reflected, and the reflected light passes through an image-forming optical system 4 to form a wafer mark M1x image WM on an imaging surface of an image pick-up device 5. In the image pick-up device 5, the mark M1x image is subjected to photoelectric conversion, and the resultant image is converted into two-dimensional digital signal rows by an A/D (analog-to-digital) converter 6.
In FIG. 5a, reference numeral 7 denotes an integrating device, for setting, as illustrated in FIG. 5b, a processing window Wp with respect to wafer mark image WM, converted into a digital signal by A/D converter 6, and performing a movement averaging operation along the Y dimension in FIG. 5b in the aforementioned window to convert the two-dimensional image signal to a one-dimensional digital signal row S(x).
In the same figure, reference numeral 8 denotes a position detector in which pattern matching is performed using a previously stored template pattern with respect to the one-dimensional signal row S(x) output from the integrating device 7. The template pattern which matches most closely with the S(x) address position is output to the CPU 9. Since the output signal represents a mark position with reference to an image pick-up plane of the image pick-up device 5, CPU 9 computes position a.sub.x1 which is the position of wafer mark M1x along the x dimension with respect to a portion of the reticle R from the relative position of the image pick-up device 5 and reticle R previously obtained from a method which is not illustrated. This completes the measurement for the first measurement shot area along the x dimension. Then, CPU 9 measures the position ay1 along the y dimension of the wafer mark M1y with respect to reticle R using the same process employed to measure the displacement along the x dimension.
The CPU 9 causes stage 11 to move to the position of a second measurement shot area S2 to measure the position of wafer marks M.sub.2x and M.sub.2y in the x and y dimensions as it has been done for the first measurement shot area S1. The same measurements are performed for the remaining predetermined number of measurement shot areas, n, (n=4 in the example of FIG. 6), and the measured positions for each of the shot areas are stored as a.sub.xi, a.sub.yi (where i=1, 2 . . . , n).
Then, based on the obtained position of each measurement shot area, the CPU 9 aligns the wafer W relative to the reticle R in the following way. First, a preassigned mark position d.sub.i of the ith measurement shot area is found by the formula EQU d.sub.i =[d.sub.xi, d.sub.yi ].sup.T,
where d.sub.xi represents the preassigned position of the ith shot area along the x dimension, d.sub.yi represents the preassigned position of the ith shot area along the y dimension, and T indicates that the matrix [d.sub.xi, d.sub.yi ] is transposed. The preassigned position d.sub.i is superimposed by correction and conversion onto the actual mark position a.sub.i of the ith measurement short area found by the formula EQU a.sub.i =[a.sub.xi, a.sub.yi ].sup.T
which is obtained by wafer mark measurements. As a result, the relationship between a correction position g.sub.i of the ith short area, including a correction remainder e.sub.i of the ith shot area (e.sub.i =[e.sub.xi, e.sub.yi ].sup.T), obtained by the formula EQU g.sub.i =[g.sub.xi, g.sub.yi ].sup.T =[a.sub.xi +e.sub.xi, a.sub.yi +e.sub.yi ].sup.T,
and d.sub.i is expressed by formula (1), EQU g.sub.i =Ad.sub.i +S (1)
so as to allow computation of the conversion parameters A, S such that the sum of the squares of the correction remainder e.sub.i is a minimum, where e.sub.i is the correction of ith shot area in the x and y dimensions, e.sub.i is the correction remainder of the ith shot area along the x dimension, e.sub.yi is the correction remainder of the ith shot area along the y dimension, T indicates that the matrices [a.sub.xi, a.sub.yi ] and [e.sub.xi, e.sub.yi ] are transposed, g.sub.xi is the correction position of the ith shot area along the x dimension, g.sub.yi is the correction position of the ith shot area along the y dimension, and T also indicates that the matrix [a.sub.xi +e.sub.xi, a.sub.yi +e.sub.yi ] is transposed. Based on the conversion parameters A, S, the CPU 9 computes the correction position g.sub.i in accordance with formula (1) to allow the XY stage 11 to be driven in accordance with the correction position g.sub.i. This allows step-and-repeat operations to be performed which minimizes the difference between the measured mark position and designed mark position, so that exposure of all shot areas formed on wafer W is performed.
Here, A and S are defined as in formula (2): ##EQU1##
where .alpha.x and .alpha.y denote, respectively, the expansion or contraction of each wafer in the x and y dimensions; .theta..sub.x and .theta..sub.y denote respectively the rotation component of the x and y coordinate axes of the shot arrangement from the preassigned x and y coordinate axes of the shot arrangement as shown by .theta. and .theta.+.omega. in FIG. 8 of U.S. Pat. No. 5,153,678, which is hereby incorporated by reference thereto; s denotes the displacement of the entire wafer from the preassigned position to the measured position, where S.sub.x denotes the displacement of the entire wafer along the x dimension from the preassigned position to the measured position, and S.sub.y denotes the displacement of the entire wafer along the y dimension from the preassigned position to the measured position.
According to this method, aligning is performed using a limited number of sample shots, and not by measuring the displacement of all the exposure shots, so that throughput of the device is increased. However, although the relationship expressed by formula (1) is a linear expression representing error components of parallel (translational) movement, rotation, and expansion and contraction of the wafer W, there are some wafers to be processed in the actual semiconductor production process which are partly deformed, so that precise alignment of the entire wafer cannot be obtained by a linear expression.